Vhdl Port Map Assignment Ancient

Variables - VHDL Example

Variables in VHDL act similarly to variables in C. Their value is valid at the exact location in the code where the variable is modified. Therefore, if a signal uses the value of the variable before the assignment, it will have the old variable value. If a signal uses the value of the variable after the assignment it will have the new variable value.

Rules of Variables:

  • Variables can only be used inside processes
  • Any variable that is created in one process cannot be used in another process
  • Variables need to be defined after the keyword process but before the keyword begin
  • Variables are assigned using the := assignment symbol
  • Variables that are assigned immediately take the value of the assignment

The most important thing to understand is that variables immediately take the value of their assignment. Here's an example that shows one useful way to use variables: storing data for temporary use. It uses a case statement and the ampersand (&) concatenation operator.

VAR_CASE : process (i_clk) variable v_Choices : std_logic_vector(1 downto 0); begin v_Choices := i_select_1 & i_select_2; -- concatenation case v_Choices is when "00" => o_data <= "0001"; when "01" => o_data <= "0010"; -- ETC

In the previous example, we concatenated the two signals so that they could be used in the case statement. The variable v_Choices was immediately available for use as soon as it was assigned. Let's look at another example. The example below is more comprehensive and demonstrates how variables immediately take the value of their assignment. The signals r_Var_Copy1 and r_Var_Copy2 appear to be the same, but r_Var_Copy2 is never able to get to 5 before it is reset.

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity variable_ex is port ( i_clk : in std_logic; o_done : out std_logic ); end variable_ex; architecture rtl of variable_ex is signal r_Done : std_logic := '0'; signal r_Var_Copy1 : natural range 0 to 5 := 0; signal r_Var_Copy2 : natural range 0 to 5 := 0; begin EX_VAR : process (i_clk) variable v_Count : natural range 0 to 5 := 0; begin if rising_edge(i_clk) then v_Count := v_Count + 1; r_Var_Copy1 <= v_Count; if v_Count = 5 then r_Done <= '1'; v_Count := 0; else r_Done <= '0'; end if; r_Var_Copy2 <= v_Count; end if; end process EX_VAR; o_done <= r_Done; end rtl;

In order to simulate our design, we need to create a testbench. Also, variables can be a bit tricky to display in simulation. If you are using Modelsim, read more about how to see your variables in Modelsim's waveform window.

Testbench:

library ieee; use ieee.std_logic_1164.all; entity variable_ex_tb is end variable_ex_tb; architecture behave of variable_ex_tb is component variable_ex port ( i_clk : in std_logic; o_done : out std_logic ); end component variable_ex; constant c_CLK_PERIOD : time := 10 ns; signal r_CLK : std_logic := '0'; signal w_DONE : std_logic; begin UUT : variable_ex port map ( i_clk => r_CLK, o_done => w_DONE ); r_CLK <= not r_CLK after c_CLK_PERIOD/2; end behave;

Variables Example Testbench Waveform

The example above demonstrates how variables act differently from signals. The signals r_Var_Copy1 and r_Var_Copy2 appear to be the same, but r_Var_Copy2 is never able to get to 5 before it is reset.

Read more about how variables and signals are different

The following content has been imported from Legacy Help systems and is in the process of being checked for accuracy.

VHDL is a hardware description language (HDL). It contains the features of a conventional programming language, a classical PLD programming language, and a netlist, as well as design management features.
VHDL is a large language and it provides many features. This reference does not attempt to describe the full language
- rather it introduces enough of the language to enable useful design.
The VHDL Synthesis engine supports most of the VHDL language, however, some sections of the language have meanings that are unclear in the context of logic design
- the file operations in the package "textio", for example. The exceptions and constraints on the Synthesizer's VHDL support are listed in the topics 'Unsupported Constructs', 'Ignored Constructs', and 'Constrained Constructs'.
The VHDL Synthesizer uses the VHDL'93 version of VHDL. This version is basically a superset of the previous standard VHDL'87.

Notation Conventions

VHDL is not case-sensitive, so a design description can contain UPPERCASE or lowercase text.  In this reference, examples are all lowercase. VHDL reserved words in both the text and the examples are bold, for example :
entity counter is
port (clk, reset: in bit; sum: out integer);
end counter ;

bold

In examples, bold type indicates a reserved word. In the example above, entity, is, port, in, out, and end are all reserved words

plain-text

Regular plain type represents a user-definable identifier or another VHDL construct.  Reserved words cannot be used as user-defined identifiers. In the example above, the name "sum" is a user-defined identifier.

Structure of a VHDL Design Description
The basic organization of a VHDL design description is shown below:

A package is an optional statement for shared declarations. An entity contains declarations of the design I/O, and an architecture contains the description of the design. A design may contain any number of package, entity and architecture statements. Most of the examples in this guide use a single entity-architecture pair.
An architecture contains concurrent statements. Concurrent statements (like netlists and classic PLD programming languages) are evaluated independently of the order in which they appear. Values are passed between statements by signals ; an assignment to a signal ( <= ) implies a driver. A signal can be thought of as a physical wire (or bundle of wires).
The most powerful VHDL constructs occur within sequential statements. These must be placed inside a particular concurrent statement, the process statement, or inside a function or procedure .
Sequential statements are very similar to programming language statements: they are executed in the order they are written (subject to if statements, return statements, etc.). Values are held in variables and constants . Signals are used to pass values in and out of a process , to and from other concurrent statements (or the same statement).
Several concepts are important to the understanding of VHDL.  They include: the distinction between concurrent statements and sequential statements, and the understanding that signals pass values between concurrent statements, and variables pass values between sequential statements.
Sequential statements in VHDL refer to statement ordering, not to the type of logic compiled. Sequential statements may be used to compile both combinational and sequential logic.
VHDL can be written at three levels of abstraction: structural, data flow, and behavioral. These three levels can be mixed.
The following topics: Structural VHDL, Data Flow VHDL, and Behavioral VHDL, introduce the structural, data flow, and behavioral design methods and show VHDL code fragments that are written at each level of abstraction.
Variations of the following design are used to illustrate the differences:
entity hello is
port (clock, reset : in boolean; char : out character);
end hello;

architecture behavioral of hello is
constant char_sequence : string := "hello world";
signal step : integer range 1 to char_sequence'high := 1;
begin
-- Counter
process (reset,clock)
begin
if reset then
step <= 1;
elsif clock and clock'event then
if step = char_sequence'high then
step <= 1;
else
step <= step
+ 1;
end if ;
end if ;
end process ;

-- Output Decoder
char <= char_sequence(step);
end behavioral ;
This design compiles to a simple waveform generator with two inputs (clock and reset) and eight outputs. The output sequences through the ASCII codes for each of the eleven characters in the string "hello world". The codes change some logic delay after each rising edge of the clock. When the circuit is reset, the output is the code for 'h' -- reset is asynchronous.
Structural VHDL
A structural VHDL design description consists of component instantiation statements, which are concurrent statements. For example:
u0: inv port map (a_2, b_5);
This is a netlist-level description. As such, you probably do not want to type many statements at the structural level. Schematic capture has long been known as an easier way to enter netlists.
Structural VHDL simply describes the interconnection of hierarchy. Description of the function requires the data flow or behavioral levels. Component instantiation statements are useful for sections of design that are reused, and for integrating designs.
The design in the following example has been partitioned into two instantiated components. Note that the components are declared but not defined in the example. The components would be defined as entity/architecture pairs.
entity hello is
port (clock, reset : in boolean; char : out character);
end hello;

architecture structural of hello is
constant char_sequence : string := "hello world";
subtype short is integer range 1 to char_sequence'high;
signal step : short;
component counter
port (clock, reset : in boolean; num : out short);
end component ;
component decoder
port (num : in short ; res : out character);
end component ;
begin
U0 : counter port map (clock,reset,step);
U1 : decoder port map (step,char);
end structural;
This is useful if counter and decoder had been previously created and compiled into two PALs. The availability of a larger PAL allows you to integrate the design by instantiating these as components and compiling for the larger device.
Data Flow VHDL
Another concurrent statement is the signal assignment. For example:
a <= b and c;
m <= in1 when a1 else in2;
Assignments at this level are referred to as data flow descriptions. They are sometimes referred to as RTL (register-transfer-level) descriptions.
This example could be rewritten as :
entity hello is
port (clock, reset: in boolean; char : out character);
end hello;

architecture data_flow of hello is
constant char_sequence : string := "hello world";
signal step0, step1 :integer range 1 to char_sequence'high := 0;
begin
-- Output decoder
char <= char_sequence(step1);

-- Counter logic
step1 <= 1 when step0 = char_sequence'high else step0
+ 1;

-- Counter flip flops
step0 <= 1 when reset else
step1 when clock and clock'event;
end data_flow;
In data flow descriptions combinational logic is described with the signal assignment ( <= ). There is no register assignment operator; sequential logic is inferred from incomplete specification (of step0) as in the example above.
Behavioral VHDL
The most powerful concurrent statement is the process statement. The process statement contains sequential statements and allows designs to be described at the behavioral level of abstraction. For example :
process (insig)
variable var1: integer; -- variable declaration
begin
var1:= insig; -- variable assignment
var1:= function_name(var1
+ 1); -- function call
end process ;
In hardware design the process statement is used in two ways: one for combinational logic and one for sequential logic. To describe combinational logic the general form of the process statement is :
process (signal_name, signal_name, signal_name,......)
begin
.....
end process ;
and the general form for sequential logic :
process (clock_signal)
begin
if clock_signal and clock_signal'event then
....
end if ;
end process ;
For combinational logic there is a list of  all process input signals after the keyword process . For sequential logic there is either: (a) no sensitivity list but there is a wait statement; or (b) a sensitivity list containing the clock and the statements are within an if statement.
It is illegal in VHDL for a process to have both a sensitivity list and a wait statement. To have neither implies no logic.
Our example could be viewed as two processes: one for the sequential counter, and one of the combinatorial decoder :
entity hello is
port (clock, reset : in boolean; char : out character);
end hello;

architecture behavioral of hello is
constant char_sequence : string := "hello world";
signal step : integer range 1 to char_sequence'high := 1;
begin
counter : process (reset, clock)
begin
if reset then
step <= 1;
elsif clock and clock'event then
if step = char_sequence'high then
step <= 1;
else
step <= step
+ 1;
end if ;
end if ;
end process ;

decoder : process (step)
begin
char <= char_sequence(step);
end process ;
end behavioral;

VHDL Types
VHDL contains the usual programming language data types, such as:

  • boolean
  • character
  • integer
  • real
  • string

These types have their usual meanings. In addition, VHDL has the types:

The type bit can have a value of '0' or '1'. A bit_vector is an array of bits. (Similarly, a string is an array of characters in VHDL just as it is in Pascal).
Most electrical engineers use the IEEE 1164-standard-logic types in place of bit and bit_vector.

  • std_logic
  • std_logic_vector

These are declared in the IEEE library in package std_logic_1164
To make these declarations visible, an entity that uses these types is prefixed with a library declaration and a use clause:
library ieee;
use ieee.std_logic_1164. all ;
Definitions for all of the predefined types can be found in the file std.vhd , which contains the package standard.
The type of a variable , signal , or constant (which are collectively called objects) determines the operators that are predefined for that object. For hardware design, the type also determines the number -- and possibly the encoding scheme used -- for the wires that are implemented for that object.
Type-checking is performed during analysis. Types are used to resolve overloaded subprograms. Users may define their own types, which may be scalars, arrays, or records.
VHDL also allows subtypes. This is simply a mechanism to define a subset of a type. More information on the impact of types and subtypes on synthesis is contained in the topic 'Synthesis of VHDL Types'.
Simulatable,ButNotNecessarilySynthesizable
This section is primarily for experienced VHDL simulation users who have VHDL code that has been developed using a VHDL simulator.
VHDL is a standard, how can there be a problem? Many VHDL models are not suitable for synthesis, such as high level performance models, environment models for stimulus/response, or system models including software,  hardware, and physical aspects.
Synthesis assumes that the VHDL code describes the logic of a design, and not some model of the design. This assumption puts additional constraints on the programmer. Most of the remainder of this guide describes how to program in VHDL within these constraints.
A design description may be correctly specified in English, but may have no practical hardware implementation (e.g. H.G.Wells' Time Machine). The same is true for a design specified in VHDL, which may have no practical implementation. Just because its written in a Hardware Description Language doesn't mean it describes realizable hardware!
For example, suppose you have a VHDL simulation model of a PAL, lets say the model configures itself from a JEDEC file during simulation initialization. The model actually simulates the programming and logic of the PAL. It describes more than just the hardware, the model also describes the manufacturing step when the PAL was programmed. A synthesizable VHDL model would only describe the component function and not the earlier manufacturing step.

SomeOtherIssues

Hardware design adds several additional constraints such as gated clocks. These are not a constraint in a simulation where values may be written to computer memory without concern for electrical glitches. Hardware design requires care be taken in controlling the clocking of memory elements.
A simulation model may also describe the timing characteristics of a design. These are ignored by the synthesis tool, which considers timing a result of the hardware realization of the design. A VHDL model that depends on the timing for correct operation may not synthesize to the expected result.
A simulation model may use enumerated types to:

  • represent the encoding of a group of wires (e.g. load store execute), perhaps as part of a state machine description
  • represent the electrical characteristic on a single wire ( e.g. high impedance, resistive, strong), as well as the state  of the simulation (unknown, uninitialized)

Within VHDL, a synthesis system has no way to distinguish the meaning in each case. The synthesizer assumes the encoding representation for enumerated types unless the encoding is explicitly specified using the attribute 'enum_encoding'.

PLD Programming using VHDL
VHDL is a large language.  It is an impractical task to learn the whole language before trying to use it. Fortunately, it is not necessary to learn the whole language in order to use VHDL ( the same is true of any computer or even human language).  This section presents a view of VHDL that should be familiar to users of classic PLD programming languages.
Just as in PLD programming, the design I/O, combinational logic, sequential logic, and state machines can be described. Initially, only signals of type std_logic and std_logic_vector (a 1 dimensional array of std_logic) will be considered. These types allow you to do logical operations (and, or...) and relational operations (equal, greater than,....).
Design I/O
Design I/O is described using a port statement.  Ports may have mode IN, OUT , INOUT or BUFFER. The mode describes the direction of data flow.  The default mode of a port is IN. Values may be assigned to ports of mode OUT and INOUT or BUFFER, and read from ports mode IN and INOUT or BUFFER. Port statements occur within an entity. For example :
entity ent1 is
port (a0,a1,b0,b1 : in std_logic; c0, c1 : out std_logic);
end ent1;

entity ent2 is
port (a,b : std_logic_vector(0 to 5);
sel : std_logic; c : out std_logic_vector(0 to 5)) ;
end ent2;
INOUT and BUFFER are used to specify routing on ports. An INOUT port specifies bi-directional dataflow, and a BUFFER port is a unidirectional OUT that you can read from. INOUT describes a signal path that runs through a pin and back into the design: "pin feedback" in PLDs or an IO block in some FPGAs. BUFFER describes a signal path that drives an output buffer to a pin and internal logic: "register feedback" in PLDs or internal routing in FPGAs. INOUT is required to specify pin feedback. Register feedback may be specified using BUFFER or using OUT and an extra signal.
It is also a convention to use another standard, IEEE 1164. To use this standard, the following two lines are written before each entity (or package) to provide visibility to the definition of 'std_logic'. This is not required, it's just a convention.
library ieee;
use ieee.std_logic_1164. all ;
Combinational Logic
Combinational logic may be described using concurrent statements, just like equations in PLD languages. Concurrent statements occur within an architecture. Note that an architecture references an entity.
The equations assign values to signals. Ports are examples of signals; all signals must be declared before they are used. A two bit adder can be described using boolean equations :
architecture adder of ent1 is
signal d, e : std_logic;
begin
d    <= b0 and a0;
e    <= b1 xor a1;
c0   <= (b0 and not a0) or ( not b0 and a0);
c1   <= (e and not d) or ( not e and d);
end adder;
Conditional assignment can also be performed.  Here conditional assignment is used to build a mux:
architecture mux1 of ent2 is
begin
c <= a when sel = '1' else b;
end mux1;
Note that omitting the ' else b' above would specify a latch:
c <= a when sel = '1';
because this would then have the same meaning as:
c <= a when sel = '1' else c;
The meaning is different to some PLD languages, which may assume a default else to be 'zero', or perhaps 'don't care'. VHDL'93 is also different from VHDL'87 which required the else to be present.
Generate is a concurrent looping structure. This construct allows another possible implementation of the mux. This example also illustrates selecting elements of arrays:
architecture mux2 of ent2 is
begin
for i in 0 to 5 generate
c(i) <= (a(i) and sel) or (b(i) and not sel);
end generate ;
end mux2;
Registers and Tri-state
VHDL does not contain a register assignment operator; registers are inferred from usage. Therefore, a D latch could be described :
q <= d when clk = '1';
and a D flip flop :
q <= d when clk = '1' and clk'event
and a D flip flop with asynchronous reset:
q <= '0' when rst = '1' else d when clk = '1' and clk'event
In practice, the clk'event expression is a little cumbersome. This can be improved upon by using the rising_edge () function from std_logic_1164. In the following example output registers are added to the combinational adder:
library ieee;
use ieee.std_logic_1164. all ;
entity counter is
port (a0,a1,b0,b1,clk : in std_logic; c0, c1 : out std_logic);
end counter;

architecture adder_ff of counter is
signal d, e, f, g  : std_logic;
begin
d  <= b0 and a0;
e  <= b1 xor a1;
f  <= (b0 and not a0) or ( not b0 and a0);
g  <= (e and not d) or ( not e and d);
c0 <= f when rising_edge(clk);
c1 <= g when rising_edge(clk);
end adder_ff;
Tristates can be added in much the same way as flip flops, by using a conditional assignment of 'Z' (here controlled by an input oe):
architecture adder_ff_tri of counter is
signal d, e, f, g, h, i  : std_logic;
begin
d  <= b0 and a0;
e  <= b1 xor a1;
f  <= (b0 and not a0) or ( not b0 and a0);
g  <= (e and not d) or ( not e and d);
h  <= f when rising_edge(clk);
i  <= g when rising_edge(clk);
c0 <= h when oe = '1' else 'Z';
c1 <= i when oe = '1' else 'Z';
end adder_ff_tri;
Procedures can be used to make the intent of the design a little clearer, such as moving the combinational logic into a procedure. Notice that procedures contain programming language like 'sequential statements' and that intermediate values in the example below are held in variables. Notice also that signals are assigned with "<=", and variables with ":=". Like programming languages, the order of sequential statements is important.
architecture using_procedure of counter is
signal f, g  : std_logic;
procedure add ( signal a0,a1,b0,b1 : std_logic;
signal c0,c1 : out std_logic) is
variable x,y : std_logic;
begin
x    := b0 and a0;
y    := b1 xor a1;
c0   <= (b0 and not a0) or ( not b0 and a0);
c1   <= (y and not x) or ( not y and x);
end ;
begin
add ( a0, a1, b0, b1, f, g);
c0 <= f when rising_edge(clk);
c1 <= g when rising_edge(clk);
end using_procedure;
State Machines
There is no state transition view in VHDL, however, it does support a behavioral view. This allows design description in a programming-language-like way. Sequential statements may also occur in processes.
q <= d when rising_edge(clk);
An exactly equivalent statement is:
process (clk)
begin
if rising_edge(clk) then
q <= d;
end if ;
end process ;
The process statement may contain many sequential statements. This simple behavioral description is very like a state machine description in a classic PLD language.
library ieee;
use ieee.std_logic_1164. all ;
entity ent5 is
port (clk,reset : in std_logic;
p : buffer std_logic_vector(1 downto 0));
end ent5 ;

architecture counter1 of ent5 is
begin
process (clk, rst)
begin
if reset = '1' then
p <= "00";
elsif rising _edge(clk) then
case p is
when "00" => p <= "01";
when "01" => p <= "10";
when "10" => p <= "11";
when "11" => p <= "00";
end case ;
end if ;
end process ;
end counter1 ;
Although the process statement can be used as a way to describe state machines, it more generally allows behavioral modeling of both combinational and sequential logic.
It is strongly recommended that you read the topics 'Programming Sequential Logic' and 'Programming Finite State Machines' before attempting to write process statements; it is important to understand the impact of the wait statement on signals and variables in the process statement.
Hierarchy
In VHDL each entity and architecture combination defines an element of hierarchy. Hierarchy may be instantiated using components. Since there is a default binding between a component and an entity with the same name, a hierarchical design instantiating Child in Parent looks like:
---Child
library ieee;
use ieee.std_logic_1164. all ;

entity Child is
port (I : std_logic_vector(2 downto 0) ;
O : out std_logic_vector(0 to 2));
end Child;

architecture behavior of Child is
begin
o <= i;
end ;

---Parent
use ieee.std_logic_1164. all ;
entity Parent is
port (a : std_logic_vector(7 downto 5);
v : out std_logic_vector( 1 to 3));
end Parent;

architecture behavior of Parent is
-- component declaration , bound to Entity Child above
component Child
port (I : std_logic_vector(2 downto 0) ;
O : out std_logic_vector(0 to 2));
end component ;
begin
-- component instantiation
u0 : Child port map (a,v);
end ;
Hierarchy also allows VHDL design partitioning, reuse, and incremental testing. VHDL synthesis incorporates some additional semantics of hierarchy; including controlling the logic optimize granularity, hierarchical compile, and instantiating silicon specific components as shown below.
---Parent
library ieee;
use ieee.std_logic_1164. all ;
entity Parent is
port (a,en : std_logic_vector(2 downto 0);
v : out std_logic);
end Parent;

architecture behavior of Parent is
-- component declaration , unbound
-- ASSUMES 'TriBuf' and 'Pullup' are silicon specific components
-- defined by some downstream tool.
component TriBuf is
port (I,T : std_logic ; O : out std_logic);
end component ;
component Pullup is
port (O : out std_logic);
end component ;
signal tri_net : std_logic;
begin
-- component instantiations
u0 : TriBuf port map (a(0), en(0), tri_net);
u1 : TriBuf port map (a(1), en(1), tri_net);
u2 : TriBuf port map (a(2), en(2), tri_net);
u3 : Pullup port map (tri_net);
v <= tri_net;
end ;
Types
The use of types other than 'std_logic' and 'std_vector_logic' can make your design much easier to read. It is good programming practice to put all of your type definitions in a package, and make the package contents visible with a use clause. For example:
package type_defs is
subtype very_short is integer range 0 to 3;
end type_defs;

library ieee;
use ieee.std_logic_1164. all ;
use work.type_defs. all ;

entity counter2 is
port (clk, reset : std_logic; p : buffer very_short);
end counter2 ;

architecture using_ints of counter2 is
begin
process (clk,reset)
begin
if reset = '1' then
p <= 0;
elsif rising_edge(clk) then
p <= p
+ 1;
end if ;
end process ;
end ;
In this example, type integer has been used because the "+" operator is defined for integers, but not for std_logic_vectors.
Sometimes there are other packages written by third parties that you can use, such as the Synopsys packages included with the Synthesizer. One of these packages defines a "+" operation between a std_logic_vector and an integer. Using this package the example can be rewritten:
library ieee;
use ieee.std_logic_1164. all ;
use ieee.std_logic_unsigned. all ;

entity counter2 is
port (clk, reset : std_logic;
p : buffer std_logic_vector(1 downto 0));
end counter2 ;

architecture using_ints of counter2 is
begin
process (clk,reset)
begin
if reset = '1' then
p <= "00";
elsif rising_edge(clk) then
p <= p
+ 1;
end if ;
end process ;
end ;
It is a convention that the Synopsys packages be placed in the IEEE library, however, they are not an IEEE standard. To add these packages to the IEEE library use the lib alias compile option to specify ieee.vhd and synopsys.vhd.
Compiling
You can compile each design unit (an entity and an architecture) one at a time and link the results with some downstream tool, or you can compile your whole design in one pass. The former is probably the best approach during design development, the latter is the easiest if you are importing a pre-existing design.
When compiling the whole design in one pass there can be a problem due to the constraints of downstream tools if the compiled data format is Open Abel 2. There is no problem if the complied data format is EDIF or DSL.  The problem may occur with large designs and the solution requires that the design be compiled in partitions of no more than 5000 compiled gates as described below.
The compile and link methodology for EDIF and DSL allows any compile granularity as long as the downstream tool supports linking of multiple files, this linking is usually automatic, when the linker encounters an undefined component it assumes the component is defined in a file of the same name as the component.  When compiling lower levels it may be necessary to inhibit IO buffer insertion with a compile option.
It is possible to write VHDL code where the logic of a design unit depends upon another design unit. For example if generics, or ports of an unconstrained array type, or signals declared in packages are used.  In this case the parent and child must be compiled at the same time, this case does occur but is not the most common usage.

Considerations when theCompiledDataFormat is Open Abel 2

Before compiling a design, you should consider the compile granularity. It is uncommon to compile a large design in one big "Partition". Partitioning a design into several Partitions of  500 to 5000 output gates each is most common.
A Partition may consist of one or more VHDL entities or architecture pairs and may be contained in one or more .vhd files. The method for specifying file names is described in the documentation for the software that calls the Synthesizer's compiler. Each Partition compiles to one output netlist file. Note that specifying the logic compile granularity is distinct from specifying the logic optimize granularity.
To compile a Partition, do the following :

  • specify the files(s)
  • specify the top level of this Partition
  • compile VHDL

Several Partitions may be compiled in any order, then linked with a netlist linker.
For each Partition:
{
/* do one Partition* /
a) specify files(s)
b) specify the top level of this Partition
c) compile VHDL
}
Link the output files.
Choose a Partition size of 500 to 5000 output gates because :

  • Smaller Partitions give faster compiles for design iterations.
  • Some downstream tools exhibit performance constraints with large Partitions.

This partitioning is important to your success. If the design is not your design and you don't know how much logic (output gates) it contains, then try some tests on parts of the design before selecting the partitions. Not partitioning a large design is probably a bad choice. Note, however, that partitions of 500 gates are not always required; sometimes a Partition just connects other Partitions and contains no logic.
There is a special case in partitioning for synthesis. If a VHDL component instantiation uses 'generic map', the parent and child must be compiled in the same Partition. The Parent is the Architecture containing the instantiation, and Child is the instantiated Entity. Because generic map implies different logic for each instance, it is possible to have a case where the same Child is compiled in several different Partitions.

Debugging
A very personal issue
- here are some suggestions for debugging the specification and implementation of your design.

SystemLevelSimulation

Simulate your VHDL design before synthesis using a third party VHDL simulator. This allows you to verify the specification of your design. If you don't have a VHDL simulator, run the Synthesizer with the compile option optimize set to zero (to minimize compile time), and simulate the output with your equation or gate level simulator.

Hierarchy

Partition your design into entity/architecture references as components. Compile each entity separately. Simulate using a third party equation or netlist simulator to verify functionality.
Check the size of the logic in this module. Is it about what you expected?
Using hierarchy to represent the modules of your design will result in faster and better optimization, and may allow you to reuse these design units in future designs.

Attribute 'critical'

Critical forces a signal to be retained in the output description. This allows you to trace a VHDL signal using your third party equation or netlist simulator.
The name of the VHDL signal will be maintained
-  but may be prefixed with instance, block labels, or package names, and suffixed with a "_n", if it represents more than one wire.

Log File

This file contains additional information about inferred logic structures. The information is printed on a per process basis, indicating the inferred structure, type of any control signals, and a name.
flip flop [type] <name>  bit
latch [type] <name>  bit
tristate <name>  bit
critical <name>  bit
comb fb <name>  bit
macrocell <name>

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